Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros

This work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads ( $\text{C}_{\text {L}}\text{s}$ ). At the heart proposed is new frequency compensation (FCT) relies on low-frequency left-half-plane zeros to allow operate for desired closed-loop behavior. In this work, classical gain-stages (i.e., differential pair and common source transistors) are used fully-differential 2-, 3-, 4- 5-stage OTAs. The 2-to-4-stage designs have been fabricated in TSMC 65 nm process measurement results show 2-stage achieving 50 dB with {L}}$ -drivability ratio {L,max}}/\text{C}_{\text {L,min}}$ ) notation="LaTeX">$10,000\times $ , 3-stage 70 notation="LaTeX">$1,000,000\times 4-stage 90 . 10-to-1000-time improvement state-of-the-art, as highest reported date notation="LaTeX">$1000\times Accordingly, OTAs can cover wider applications than any other works.